View AD602_98041.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
FEATURES Two Channels with Independent Gain Control "Linear in dB" Gain Response Two Gain Ranges: AD600: 0 dB to +40 dB AD602: -10 dB to +30 dB Accurate Absolute Gain: 0.3 dB Low Input Noise: 1.4 nV/Hz Low Distortion: -60 dBc THD at 1 V Output High Bandwidth: DC to 35 MHz (-3 dB) Stable Group Delay: 2 ns Low Power: 125 mW (max) per Amplifier Signal Gating Function for Each Amplifier Drives High Speed A/D Converters MIL-STD-883 Compliant and DESC Versions Available APPLICATIONS Ultrasound and Sonar Time-Gain Control High Performance Audio and RF AGC Systems Signal Measurement
C1HI C1LO VG
Dual, Low Noise, Wideband Variable Gain Amplifiers AD600/AD602*
FUNCTIONAL BLOCK DIAGRAM
GAT1 SCALING REFERENCE
PRECISION PASSIVE INPUT ATTENUATOR
GATING INTERFACE
A1OP
GAIN CONTROL INTERFACE
RF2 2.24k (AD600) 694 (AD602) -22.08dB -30.1dB -36.12dB -42.14dB RF1 20
0dB -6.02dB -12.04dB -18.06dB A1HI 500 A1LO
62.5 R - 2R LADDER NETWORK
FIXED GAIN AMPLIFIER
41.07dB (AD600) 31.07dB (AD602)
A1CM
PRODUCT DESCRIPTION
The AD600 and AD602 dual channel, low noise variable gain amplifiers are optimized for use in ultrasound imaging systems, but are applicable to any application requiring very precise gain, low noise and distortion, and wide bandwidth. Each independent channel provides a gain of 0 dB to +40 dB in the AD600 and -10 dB to +30 dB in the AD602. The lower gain of the AD602 results in an improved signal-to-noise ratio at the output. However, both products have the same 1.4 nV/Hz input noise spectral density. The decibel gain is directly proportional to the control voltage, is accurately calibrated, and is supplyand temperature-stable. To achieve the difficult performance objectives, a proprietary circuit form--the X-AMP(R)--has been developed. Each channel of the X-AMP comprises a variable attenuator of 0 dB to -42.14 dB followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs, and can benefit from the use of negative feedback to precisely define the gain and dynamics. The attenuator is realized as a seven-stage R-2R ladder network having an input resistance of 100 , lasertrimmed to 2%. The attenuation between tap points is 6.02 dB; the gain-control circuit provides continuous interpolation between these taps. The resulting control function is linear in dB.
X-AMP is a registered trademark of Analog Devices, Inc. *Patented.
The gain-control interfaces are fully differential, providing an input resistance of ~15 M and a scale factor of 32 dB/V (that is, 31.25 mV/dB) defined by an internal voltage reference. The response time of this interface is less than 1 s. Each channel also has an independent gating facility that optionally blocks signal transmission and sets the dc output level to within a few millivolts of the output ground. The gating control input is TTL and CMOS compatible. The maximum gain of the AD600 is 41.07 dB, and that of the AD602 is 31.07 dB; the -3 dB bandwidth of both models is nominally 35 MHz, essentially independent of the gain. The signal-to-noise ratio (SNR) for a 1 V rms output and a 1 MHz noise bandwidth is typically 76 dB for the AD600 and 86 dB for the AD602. The amplitude response is flat within 0.5 dB from 100 kHz to 10 MHz; over this frequency range the group delay varies by less than 2 ns at all gain settings. Each amplifier channel can drive 100 load impedances with low distortion. For example, the peak specified output is 2.5 V minimum into a 500 load, or 1 V into a 100 load. For a 200 load in shunt with 5 pF, the total harmonic distortion for a 1 V sinusoidal output at 10 MHz is typically -60 dBc. The AD600J and AD602J are specified for operation from 0C to +70C, and are available in both 16-pin plastic DIP (N) and 16-pin SOIC (R). The AD600A and AD602A are specified for operation from -40C to +85C and are available in both 16-pin cerdip (Q) and 16-pin SOIC (R). The AD600S and AD602S are specified for operation from -55C to +125C and are available in a 16-pin cerdip (Q) package and are MIL-STD-883 compliant. The AD600S and AD602S are also available under DESC SMD 5962-94572.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
+625 mV, RL = 500
Parameter
= =5 V AD600/AD602-SPECIFICATIONS (Each amplifier section, at Tare+25 C, V unless V, -625 mVnoted.) , and C = 5 pF, unless otherwise noted. Specifications for AD600 and AD602 identical otherwise
A S G L
Conditions
AD600J/AD602J Min Typ Max
AD600A/AD602A Min Typ Max
Units pF nV/Hz dB dB dB
INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Noise Spectral Density1 Noise Figure Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS -3 dB Bandwidth Slew Rate Peak Output2 Output Impedance Output Short-Circuit Current Group Delay Change vs. Gain Group Delay Change vs. Frequency Total Harmonic Distortion ACCURACY AD600 Gain Error
Pins 2 to 3; Pins 6 to 7
98
RS = 50 , Maximum Gain RS = 200 , Maximum Gain f = 100 kHz
100 2 1.4 5.3 2 30
102
95
100 2 1.4 5.3 2 30
105
VOUT = 100 mV rms RL 500 f 10 MHz f = 3 MHz; Full Gain Range VG = 0 V, f = 1 MHz to 10 MHz RL= 200 , VOUT = 1 V Peak, Rpd = 1 k 2.5
35 275 3 2 50 2 2 -60
2.5
35 275 3 2 50 2 2 -60
MHz V/s V mA ns ns dBc
Maximum Output Offset Voltage3 Output Offset Variation AD602 Gain Error
0 dB to 3 dB Gain 3 dB to 37 dB Gain 37 dB to 40 dB Gain VG = -625 mV to +625 mV VG = -625 mV to +625 mV -10 dB to -7 dB Gain -7 dB to 27 dB Gain 27 dB to 30 dB Gain VG = -625 mV to +625 mV VG = -625 mV to +625 mV 3 dB to 37 dB (AD600); -7 dB to 27 dB (AD602)
0 -0.5 -1
+0.5 0.2 -0.5 10 10 +0.5 0.2 -0.5 5 5
+1 +0.5 0 50 50 +1 +0.5 0 30 30
-0.5 -0.1 -1.5
+0.5 0.2 -0.5 10 10 +0.5 0.2 -0.5 10 10
+0.5 +1.0 +0.5 65 65 +1.5 +1.0 +0.5 45 45
dB dB dB mV mV dB dB dB mV mV
0 -0.5 -1
-0.5 -0.1 -1.5
Maximum Output Offset Voltage3 Output Offset Variation GAIN CONTROL INTERFACE Gain Scaling Factor Common-Mode Range Input Bias Current Input Offset Current Differential Input Resistance Response Rate SIGNAL GATING INTERFACE Logic Input "LO" (Output ON) Logic Input "HI" (Output OFF) Response Time Input Resistance Output Gated OFF Output Offset Voltage Output Noise Spectral Density Signal Feedthrough @ 1 MHz AD600 AD602 POWER SUPPLY Specified Operating Range Quiescent Current
31.7 -0.75
32 0.35 10 15 40
32.3 2.5 1 50
30.5 -0.75
32 0.35 10 15 40
Pins I to 16; Pins 8 to 9 Full 40 dB Gain Change
33.5 2.5 1 50 50
dB/V V A nA M dB/s
0.8 2.4 ON to OFF, OFF to ON Pins 4 to 3 Pins 5 to 6 0.3 30 10 65 -80 -70 4.75 11 5.25 12.5 4.75 11 100 2.4 0.3 30 10 65 -80 -70
0.8
V V s k mV nV/Hz dB dB
400
5.25 14
V mA
NOTES 1 Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage and current noise sources. 2 Using resistive loads of 500 or greater, or with the addition of a 1 k pull-down resistor when driving lower loads 3 The dc gain of the main amplifier in the AD600 is X113; thus an input offset of only 100 V becomes an 11.3 mV output offset. In the AD602, the amplifier's gain is X35.7; thus, an input offset of 100 V becomes a 3.57 mV output offset. Specifications shown in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels. All min and max specifications guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice.
-2-
REV. A
AD600/AD602
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 V Input Voltages Pins 1, 8, 9, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Pins 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . . . 2 V Continuous . . . . . . . . . . . . . . . . . . . . . . . . . VS for 10 ms Pins 4, 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range (J) . . . . . . . . . . . 0C to +70C Operating Temperature Range (A) . . . . . . . . . -40C to +85C Operating Temperature Range (S) . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 16-Pin Plastic Package: JA = 85C/Watt 16-Pin SOIC Package: JA = 100C/Watt 16-Pin Cerdip Package: JA = 120C/Watt
PIN DESCRIPTION
Pin Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9
Function Description C1LO A1HI A1LO GAT1 GAT2 A2LO A2HI C2LO C2HI CH1 Gain-Control Input "LO" (Positive Voltage Reduces CH1 Gain). CH1 Signal Input "HI" (Positive Voltage Increases CH1 Output). CH1 Signal Input "LO" (Usually Taken to CH1 Input Ground) CH1 Gating Input (A Logic "HI" Shuts Off CH1 Signal Path). CH2 Gating Input (A Logic "HI" Shuts Off CH2 Signal Path). CH2 Signal Input "LO" (Usually Taken to CH2 Input Ground). CH2 Signal Input "HI" (Positive Voltage Increases CH2 Output). CH2 Gain-Control Input "LO" (Positive Voltage Reduces CH2 Gain). CH2 Gain-Control Input "HI" (Positive Voltage Increases CH2 Gain). CH2 Common (Usually Taken to CH2 Output Ground). CH2 Output. Negative Supply for Both Amplifiers. Positive Supply for Both Amplifiers. CH1 Output. CH1 Common (Usually Taken to CH1 Output Ground). CH1 Gain-Control Input "HI" (Positive Voltage Increases CH1 Gain).
ORDERING GUIDE Gain Range 0 dB to +40 dB 0 dB to +40 dB -10 dB to +30 dB -10 dB to +30 dB 0 dB to +40 dB 0 dB to +40 dB -10 dB to +30 dB -10 dB to +30 dB 0 dB to +40 dB -10 dB to +30 dB Temperatue Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -55C to +150C -55C to +150C Package Option1 Q-16 R-16 Q-16 R-16 N-16 R-16 N-16 R-16 Q-16 Q-16
Pin 10 A2CM Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 A2OP VNEG VPOS A1OP A1CM
Model AD600AQ AD600AR AD602AQ AD602AR AD600JN AD600JR AD602JN AD602JR AD600SQ/883B2 AD602SQ/883B3
Pin 16 C1HI
NOTES 1 N = Plastic DIP; Q= Cerdip; R= Small Outline IC (SOIC). 2 Refer to AD600/AD602 Military data sheet. Also available as 5962-9457201MPA. 3 Refer to AD600/AD602 Military data sheet. Also available as 5962-9457202MPA.
CONNECTION DIAGRAM 16-Pin Plastic DIP (N) Package 16-Pin Plastic SOIC (R) Package 16-Pin Cerdip (Q) Package
C1LO A1HI A1LO GAT1 GAT2 A2LO A2HI C2LO
1 2 A1 3 4 REF 5 6 A2 7 8
16 C1HI 15 14 13 12 A1CM A1OP VPOS VNEG
11 A2OP 10 A2CM 9 C2HI
AD600/AD602
CAUTION ESD (electrostatic discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD600/AD602
THEORY OF OPERATION
The AD600 and AD602 have the same general design and features. They comprise two fixed gain amplifiers, each preceded by a voltage-controlled attenuator of 0 dB to 42.14 dB with independent control interfaces, each having a scaling factor of 32 dB per volt. The gain of each amplifier in the AD600 is laser trimmed to 41.07 dB (X113), thus providing a control range of -1.07 dB to 41.07 dB (0 dB to 40 dB with overlap), while the AD602 amplifiers have a gain of 31.07 dB (X35.8) and provide an overall gain of -11.07 dB to 31.07 dB (-10 dB to 30 dB with overlap). The advantage of this topology is that the amplifier can use negative feedback to increase the accuracy of its gain; also, since the amplifier never has to handle large signals at its input, the distortion can be very low. A further feature of this approach is that the small-signal gain and phase response, and thus the pulse response, are essentially independent of gain. The following discussion describes the AD600. Figure 1 is a simplified schematic of one channel. The input attenuator is a seven-section R-2R ladder network, using untrimmed resistors of nominally R = 62.5 , which results in a characteristic resistance of 125 20%. A shunt resistor is included at the input and laser trimmed to establish a more exact input resistance of 100 2%, which ensures accurate operation (gain and HP corner frequency) when used in conjunction with external resistors or capacitors.
GAT1
It will help, in understanding the AD600, to think in terms of a mechanical means for moving this slider from left to right; in fact, it is voltage controlled. The details of the control interface are discussed later. Note that the gain is at all times exactly determined, and a linear decibel relationship is automatically guaranteed between the gain and the control parameter which determines the position of the slider. In practice, the gain deviates from the ideal law, by about 0.2 dB peak (see, for example, Figure 6). Note that the signal inputs are not fully differential: A1LO and A1CM (for CH1) and A2LO and A2CM (for CH2) provide separate access to the input and output grounds. This recognizes the practical fact that even when using a ground plane, small differences will arise in the voltages at these nodes. It is important that A1LO and A2LO be connected directly to the input ground(s); significant impedance in these connections will reduce the gain accuracy. A1CM and A2CM should be connected to the load ground(s).
Noise Performance
An important reason for using this approach is the superior noise performance that can be achieved. The nominal resistance seen at the inner tap points of the attenuator is 41.7 (one third of 125 ), which exhibits a Johnson noise spectral density (NSD) of 0.84 nV/Hz (that is, 4kTR) at 27C, which is a large fraction of the total input noise. The first stage of the amplifier contributes a further 1.12 nV/Hz, for a total input noise of 1.4 nV/Hz. The noise at the 0 dB tap depends on whether the input is short-circuited or open-circuited: when shorted, the minimum NSD of 1.12 nV/Hz is achieved; when open, the resistance of 100 at the first tap generates 1.29 nV/Hz, so the noise increases to a total of 1.71 nV/Hz. (This last calculation would be important if the AD600 were preceded, for example, by a 900 resistor to allow operation from inputs up to 10 V rms. However, in most cases the low impedance of the source will limit the maximum noise resistance.) It will be apparent from the foregoing that it is essential to use a low resistance in the design of the ladder network to achieve low noise. In some applications this may be inconvenient, requiring the use of an external buffer or preamplifier. However, very few amplifiers combine the needed low noise with low distortion at maximum input levels, and the power consumption needed to achieve this performance is fundamentally required to be quite high (due to the need to maintain very low resistance values while also coping with large inputs). On the other hand, there is little value in providing a buffer with high input impedance, since the usual reason for this--the minimization of loading of a high resistance source--is not compatible with low noise. Apart from the small variations just discussed, the signal-tonoise (S/ N) ratio at the output is essentially independent of the attenuator setting, since the maximum undistorted output is 1 V rms and the NSD at the output of the AD600 is fixed at 113 times 1.4 nV/Hz, or 158 nV/Hz. Thus, in a 1 MHz bandwidth, the output S/N ratio would be 76 dB. The input NSD of the AD600 and AD602 are the same, but because of the 10 dB lower gain in the AD602's fixed amplifier, its output S/N ratio is 10 dB better, or 86 dB in a 1 MHz bandwidth.
SCALING REFERENCE
PRECISION PASSIVE INPUT ATTENUATOR
GATING INTERFACE
C1HI C1LO
VG
A1OP
GAIN CONTROL INTERFACE
RF2 2.24k (AD600) 694 (AD602) -22.08dB -30.1dB -36.12dB -42.14dB RF1 20
0dB -6.02dB -12.04dB -18.06dB A1HI 500 A1LO
62.5 R - 2R LADDER NETWORK
FIXED GAIN AMPLIFIER
41.07dB (AD600) 31.07dB (AD602)
A1CM
Figure 1. Simplified Block Diagram of Single Channel of the AD600 and AD602
The nominal maximum signal at input A1HI is 1 V rms ( 1.4 V peak) when using the recommended 5 V supplies, although operation to 2 V peak is permissible with some increase in HF distortion and feedthrough. Each attenuator is provided with a separate signal "LO" connection, for use in rejecting commonmode, the voltage between input and output grounds. Circuitry is included to provide rejection of up to 100 mV. The signal applied at the input of the ladder network is attenuated by 6.02 dB by each section; thus, the attenuation to each of the taps is progressively 0, 6.02, 12.04, 18.06, 24.08, 30.1, 36.12 and 42.14 dB. A unique circuit technique is employed to interpolate between these tap points, indicated by the "slider" in Figure 1, providing continuous attenuation from 0 dB to 42.14 dB.
-4-
REV. A
AD600/AD602
The Gain-Control Interface Common-Mode Rejection
The attenuation is controlled through a differential, high impedance (15 M) input, with a scaling factor which is laser trimmed to 32 dB per volt, that is, 31.25 mV/dB. Each of the two amplifiers has its own control interface. An internal bandgap reference ensures stability of the scaling with respect to supply and temperature variations, and is the only circuitry common to both channels. When the differential input voltage VG = 0 V, the attenuator "slider" is centered, providing an attenuation of 21.07 dB, thus resulting in an overall gain of 20 dB (= -21.07 dB + 41.07 dB). When the control input is -625 mV, the gain is lowered by 20 dB (= 0.625 x 32), to 0 dB; when set to +625 mV, the gain is increased by 20 dB, to 40 dB. When this interface is overdriven in either direction, the gain approaches either -1.07 dB (= -42.14 dB + 41.07 dB) or 41.07 dB (= 0 + 41.07 dB), respectively. The gain of the AD600 can thus be calculated using the following simple expression: Gain (dB) = 32 VG + 20 where VG is in volts. For the AD602, the expression is: Gain (dB) = 32 VG + 10 (2) Operation is specified for VG in the range from -625 mV dc to +625 mV dc. The high impedance gain-control input ensures minimal loading when driving many amplifiers in multiplechannel applications. The differential input configuration provides flexibility in choosing the appropriate signal levels and polarities for various control schemes. For example, the gain-control input can be fed differentially to the inputs, or single-ended by simply grounding the unused input. In another example, if the gain is to be controlled by a DAC providing a positive only ground referenced output, the "Gain Control LO" pin (either C1LO or C2LO) should be biased to a fixed offset of +625 mV, to set the gain to 0 dB when "Gain Control HI" (C1HI or C2HI) is at zero, and to 40 dB when at +1.25 V. It is a simple matter to include a voltage divider to achieve other scaling factors. When using an 8-bit DAC having a FS output of +2.55 V (10 mV/bit) a divider ratio of 1.6 (generating 6.25 mV/ bit) would result in a gain setting resolution of 0.2 dB/ bit. Later, we will discuss how the two sections of an AD600 or AD602 may be cascaded, when various options exist for gain control.
Signal-Gating Inputs
A special circuit technique is used to provide rejection of voltages appearing between input grounds (A1LO and A2LO) and output grounds (A1CM and A2CM). This is necessary because of the "op amp" form of the amplifier, as shown in Figure 1. The feedback voltage is developed across the resistor RF1 (which, to achieve low noise, has a value of only 20 ). The voltage developed across this resistor is referenced to the input common, so the output voltage is also referred to that node. To provide rejection of this common voltage, an auxiliary amplifier (not shown) is included, which senses the voltage difference between input and output commons and cancels this error component. Thus, for zero differential signal input between A1HI and A1LO, the output A1OP simply follows the voltage at A1CM. Note that the range of voltage differences which can exist between A1LO and A1CM (or A2LO and A2CM) is limited to about 100 mV. Figure 50 (one of the typical performance curves at the end of this data sheet) shows typical commonmode rejection ratio versus frequency.
ACHIEVING 80 dB GAIN RANGE
(1)
The two amplifier sections of the X-AMP can be connected in series to achieve higher gain. In this mode, the output of A1 (A1OP and A1CM) drives the input of A2 via a high-pass network (usually just a capacitor) that rejects the dc offset. The nominal gain range is now -2 dB to +82 dB for the AD600 or -22 dB to +62 dB for the AD602. There are several options in connecting the gain-control inputs. The choice depends on the desired signal-to-noise ratio (SNR) and gain error (output ripple). The following examples feature the AD600; the arguments generally apply to the AD602, with appropriate changes to the gain values.
Sequential Mode (Maximum S/N Ratio)
In the sequential mode of operation, the SNR is maintained at its highest level for as much of the gain control range possible, as shown in Figure 2. Note here that the gain range is 0 dB to 80 dB. Figure 3 shows the general connections to accomplish this. Both gain-control inputs, C1HI and C2HI, are driven in parallel by a positive only, ground referenced source with a range of 0 V to +2.5 V.
85 80 75 70
Each amplifier section of the AD600 and AD602 is equipped with a signal gating function, controlled by a TTL or CMOS logic input (GAT1 or GAT2). The ground references for these inputs are the signal input grounds A1LO and A2LO, respectively. Operation of the channel is unaffected when this input is LO or left open-circuited. Signal transmission is blocked when this input is HI. The dc output level of the channel is set to within a few millivolts of the output ground (A1CM or A2CM), and simultaneously the noise level drops significantly. The reduction in noise and spurious signal feedthrough is useful in ultrasound beam-forming applications, where many amplifier outputs are summed.
S/N RATIO - dB
65 60 55 50 45 40 35 30 -0.5 0.0 0.5 1.0 VG 1.5 2.0 2.5 3.0
Figure 2. S/N Ratio vs. Control Voltage Sequential Control (1 MHz Bandwidth)
REV. A
-5-
AD600/AD602
A1
-40.00dB
A2
-41.07dB
INPUT 0dB
-40.00dB C1HI C1LO VG1
41.07dB
1.07dB
-42.14dB C1HI C1LO VG2
41.07dB
OUTPUT 0dB
VO1 = 0.592V
VO2 = 1.908V
VC = 0V
(a)
-0.51dB
-1.07dB
INPUT 0dB
-0.51dB C1HI C1LO VG1
41.07dB
40.56dB
-41.63dB C1HI C1LO VG2
41.07dB
OUTPUT 40dB
VO1 = 0.592V
VO2 = 1.908V
VC = 1.25V
(b)
0dB
38.93dB
INPUT 0dB
0dB C1HI VG1 C1LO
41.07dB
41.07dB
-2.14dB C1HI C1LO VG2
41.07dB
OUTPUT 80dB
VO1 = 0.592V
VO2 = 1.908V
VC = 25V
(c)
Figure 3. AD600 Gain Control Input Calculations for Sequential Control Operation
The gains are offset (Figure 4) such that A2's gain is increased only after A1's gain has reached its maximum value. Note that for a differential input of -700 mV or less, the gain of a single amplifier (A1 or A2) will be at its minimum value of -1.07 dB; for a differential input of +700 mV or more, the gain will be at its maximum value of 41.07 dB. Control inputs beyond these limits will not affect the gain and can be tolerated without damage or foldover in the response. See the Specifications Section of this data sheet for more details on the allowable voltage range. The gain is now Gain (dB) = 32 VC where VC is the applied control voltage.
+41.07dB 40.56dB +38.93dB
(3)
When VC is set to zero, VG1 = -0.592 V and the gain of A1 is +1.07 dB (recall that the gain of each amplifier section is 0 dB for VG = 625 mV); meanwhile, VG2 = -1.908 V so the gain of A2 is -1.07 dB. The overall gain is thus 0 dB (see Figure 3a). When VC = +1.25 V, VG1 = 1.25 V- 0.592 V = +0.658 V, which sets the gain of A1 to 40.56 dB, while VG2 = 1.25 V - 1.908 V = -0.658 V, which sets A2's gain at -0.56 dB. The overall gain is now 40 dB (see Figure 3b). When VC = +2.5 V, the gain of A1 is 41.07 dB and that of A2 is 38.93 dB, resulting in an overall gain of 80 dB (see Figure 3c). This mode of operation is further clarified by Figure 5, which is a plot of the separate gains of A1 and A2 and the overall gain versus the control voltage. Figure 6 is a plot of the gain error of the cascaded amplifiers versus the control voltage.
Parallel Mode (Simplest Gain-Control Interface)
A1
20dB
A2
* *
-0.56dB -1.07dB 0.592 0.625 20 1.908 1.875 60
+1.07dB
In this mode, the gain-control voltage is applied to both inputs in parallel--C1HI and C2HI are connected to the control voltage, and C1LO and C2LO are optionally connected to an offset voltage of +0.625 V. The gain scaling is then doubled to 64 dB/ V, requiring only 1.25 V for an 80 dB change of gain. The amplitude of the gain ripple in this case is also doubled, as shown in Figure 7, and the instantaneous signal-to-noise ratio at the output of A2 decreases linearly as the gain is increased (Figure 8).
Low Ripple Mode (Minimum Gain Error)
GAIN (dB)
-2.14
0 0
1.25 40
2.5 80
VC (V) 82.14
*GAIN OFFSET OF 1.07dB, OR 33.44mV
Figure 4. Explanation of Offset Calibration for Sequential Control
As can be seen in Figures 6 and 7, the output ripple is periodic. By offsetting the gains of Al and A2 by half the period of the ripple, or 3 dB, the residual gain errors of the two amplifiers can be made to cancel. Figure 9 shows the much lower gain rip ple when configured in this manner. Figure 10 plots the S/N ratio as a function of gain; it is very similar to that in the "Parallel Mode."
-6-
REV. A
AD600/AD602
90 80 70
OVERALL GAIN - dB
75 70 65
60 50 40 30 20 10 0 -10 -0.5 A1 COMBINED A2 S/N RATIO - dB 2.0 2.5 3.0
60 55 50 45 40 35 30 0.0
0.0
0.5
1.0 VC
1.5
0.2
0.4
0.6 VC
0.8
1.0
1.2
1.4
Figure 5. Plot of Separate and Overall Gains in Sequential Control
Figure 8. SNR for Cascaded Stages--Parallel Control
5 4 3 2
1.2 1.0 0.8 0.6
GAIN ERROR - dB
0.0 0.5 1.0 VC 1.5 2.0 2.5 3.0
GAIN ERROR - dB
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -0.5
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 VC
Figure 6. Gain Error for Cascaded Stages--Sequential Control
Figure 9. Gain Error for Cascaded Stages--Low Ripple Mode
5 4 3
80 75 70
2
GAIN ERROR - dB
S/N RATIO - dB
1 0 -1 -2 -3
65 60 55 50 45
-4 -5 -0.1 0 0.2 0.4 0.6 VC 0.8 1.0 1.2 40 35 0.0
0.2
0.4
0.6 VC
0.8
1.0
1.2
1.4
Figure 7. Gain Error for Cascaded Stages--Parallel Control
Figure 10. ISNR vs. Control Voltage--Low Ripple Mode
REV. A
-7-
AD600/AD602
APPLICATIONS Increasing Output Drive
The full potential of any high performance amplifier can only be realized by careful attention to details in its applications. The following pages describe fully tested circuits in which many such details have already been considered. However, as is always true of high accuracy, high speed analog circuits, the schematic is only part of the story; this is no less true for the AD600 and AD602. Appropriate choices in the overall board layout and the type and placement of power supply decoupling components are very important. As explained previously, the input grounds A1LO and A2LO must use the shortest possible connections. The following circuits show examples of time-gain control for ultrasound and for sonar, methods for increasing the output drive, and AGC amplifiers for audio and RF/IF signal processing using both peak and rms detectors. These circuits also illustrate methods of cascading X-AMPs for either maintaining the optimal S/N ratio or maximizing the accuracy of the gaincontrol voltage for use in signal measurement. These AGC circuits may be modified for use as voltage-controlled amplifiers for use in sonar and ultrasound applications by removing the detector and substituting a DAC or other voltage source for supplying the control voltage.
Time-Gain Control (TGC) and Time-Variable Gain (TVG)
The AD600/AD602's output stage has limited capability for negative-load driving capability. For driving loads less than 500 , the load drive may be increased by about 5 mA by connecting a 1 k pull-down resistor from the output to the negative supply (Figure 12).
Driving Capacitive Loads
For driving capacitive loads of greater than 5 pF, insert a 10 resistor between the output and the load. This lowers the possibility of oscillation.
GAIN-CONTROL VOLTAGE
C1LO A1HI VIN A1LO GAT1 GAT2 A2LO A2HI C2LO
1 2 A1 3 4 REF 5 6 A2 7 8
16 15 14 13 12
C1HI A1CM A1OP VPOS VNEG -5V ADDED PULL-DOWN RESISTOR +5V
1k
11 A2OP 10 A2CM C2HI
Ultrasound and sonar systems share a similar requirement: both need to provide an exponential increase in gain in response to a linear control voltage, that is, a gain control that is "linear in dB." Figure 11 shows the AD600/AD602 configured for a control voltage ramp starting at -625 mV and ending at +625 mV for a gain-control range of 40 dB. For simplicity, only the A1 connections are shown. The polarity of the gain-control voltage may be reversed and the control voltage inputs C1HI and C1LO reversed to achieve the same effect. The gain-control voltage can be supplied by a voltage-output DAC such as the AD7242, which contains two complete DACs, operates from 5 V supplies, has an internal reference of 3 V, and provides 3 V of output swing. As such it is well-suited for use with the AD600/AD602, needing only a few resistors to scale the output voltage of the DACs to the levels needed by the AD600/AD602.
CONTROL VOLTAGE, VG +625mV 0dB VOLTAGE-OUTPUT DAC A1 GAIN C1LO A1HI A1LO GAT1 GAT2 A2LO A2HI C2LO C1HI A1CM A1OP V+ V- +5V -5V VG
AD600
9
Figure 12. Adding a 1 kPull-Down Resistor Increases the X-AMP's Output Drive by About 5 mA. Only the A1 Connections Are Shown for Simplicity.
Realizing Other Gain Ranges
Larger gain ranges can be accommodated by cascading amplifiers. Combinations built by cascading two amplifiers include -20 dB to +60 dB (using one AD602), -10 dB to +70 dB (1/2 of an AD602 followed by 1/2 of an AD600), and 0 dB to 80 dB (one AD600). In multiple-channel applications, extra protection against oscillations can be provided by using amplifier sections from different packages.
An Ultralow Noise VCA
40dB -625mV
The two channels of the AD600 or AD602 may be operated in parallel to achieve a 3 dB improvement in noise level, providing 1 nV/Hz without any loss of gain accuracy or bandwidth. In the simplest case, as shown in Figure 13, the signal inputs A1HI and A2HI are tied directly together, the outputs A1OP and A2OP are summed via R1 and R2 (100 each), and the control inputs C1HI/C2HI and C1LO/C2LO operate in parallel. Using these connections, both the input and output resistances are 50 . Thus, when driven from a 50 source and terminated in a 50 load, the gain is reduced by 12 dB, so the gain range becomes -12 dB to +28 dB for the AD600 and -22 dB to +18 dB for the AD602. The peak input capability remains unaffected (1 V rms at the IC pins, or 2 V rms from an unloaded 50 source). The loading on each output, with a 50 load, is effectively 200 , because the load current is shared between the two channels, so the overall amplifier still meets its specified maximum output and distortion levels for a 200 load. This amplifier can deliver a maximum sine wave power of +10 dBm to the load.
1 2 A1 3 4 REF 5 6 A2 7 8 AD600 or AD602
16 15 14 13 12
11 A2OP 10 A2CM 9 C2HI
Figure 11. The Simplest Application of the X-AMP Is as a TGC or TVG Amplifier in Ultrasound or Sonar. Only the A1 Connections Are Shown for Simplicity.
-8-
REV. A
AD600/AD602
GAIN-CONTROL VOLTAGE VG
C1LO A1HI A1LO GAT1 VIN GAT2 A2LO A2HI C2LO
1 2 A1 3 4 REF 5 6 A2 7 8 AD600 or AD602
16 15 14 13 12 11 10 9
C1HI A1CM A1OP VPOS VNEG A2OP A2CM C2HI +5V -5V 100 50 100 VOUT
An inexpensive circuit, using complementary transistor types chosen for their low rbb, is shown in Figure 14. The gain is determined by the ratio of the net collector load resistance to the net emitter resistance, that is, it is an open-loop amplifier. The gain will be X2 (6 dB) only into a 100 load, assumed to be provided by the input resistance of the X-AMP; R2 and R7 are in shunt with this load, and their value is important in defining the gain. For small-signal inputs, both transistors contribute an equal transconductance, which is rendered less sensitive to signal level by the emitter resistors R4 and R5, which also play a dominant role in setting the gain. This is a Class AB amplifier. As VIN increases in a positive direction, Q1 conducts more heavily and its re becomes lower while that of Q2 increases. Conversely, more negative values of VIN result in the re Of Q2 decreasing, while that of Q1 increases. The design is chosen such that the net emitter resistance is essentially independent of the instantaneous value of VIN, resulting in moderately low distortion. Low values of resistance and moderately high bias currents are important in achieving the low noise, wide bandwidth, and low distortion of this preamplifier. Heavy decoupling prevents noise on the power supply lines from being conveyed to the input of the X-AMP.
Table I. Measured Preamplifier Performance
Figure 13. An Ultralow Noise VCA Using the AD600 or AD602
A Low Noise, 6 dB Preamplifier
In some ultrasound applications, the user may wish to use a high input impedance preamplifier to avoid the signal attenuation that would result from loading the transducer by the 100 input resistance of the X-AMP. High gain cannot be tolerated, because the peak transducer signal is typically 0.5 V, while the peak input capability of the AD600 or AD602 is only slightly more than 1 V. A gain of two is a suitable choice. It can be shown that if the preamplifier's overall referred-to-input (RTI) noise is to be the same as that due to the X-AMP alone (1.4 nV/ Hz), then the input noise of a X2 preamplifier must be (3/4) times as large, that is, 1.2 nV/Hz.
+5V R1 49.9 R2 174
Measurement Gain (f = 30 MHz) Bandwidth (-3 dB) Input Signal for 1 dB Compression Distortion VIN = 200 mV p-p VIN = 500 mV p-p
Value 6 250 1 HD2 HD3 HD2 HD3 0.27 0.14 0.44 0.58 1.03
Unit dB MHz V p-p % % % % nV/Hz
1F
Q1 MRF904
1F R4 42.2 VIN R5 42.2 1F
R3 562 -5V INPUT GROUND
0.1F
+5V R6 562
0.1F
100 RIN OF X AMP
System Input Noise Spectral Density (NSD) (Preamp plus X-AMP) Input Resistance Input Capacitance Input Bias Current Power Supply Voltage Quiescent Current
1.4 15 150 5 15
k pF A V mA
A Low Noise AGC Amplifier with 80 dB Gain Range
OUTPUT GROUND
Q2 MM4049 R7 174 R8 49.9 -5V
1F
Figure 14. A Low Noise Preamplifier for the AD600 and AD602
Figure 15 provides an example of the ease with which the AD600 can be connected as an AGC amplifier. A1 and A2 are cascaded, with 6 dB of attenuation introduced by the 100 resistor R1, while a time constant of 5 ns is formed by C1 and the 50 of net resistance at the input of A2. This has the dual effect of (a) lowering the overall gain range from {0 dB to 80 dB} to {6 dB to 74 dB} and (b) introducing a single-pole low-pass filter with a -3 dB frequency of about 32 MHz. This ensures stability at the maximum gain for a slight reduction in the overall bandwidth. The capacitor C4 blocks the small dc offset voltage at the output of A1 (which might otherwise saturate A2 at its maximum gain) and introduces a high pass corner at about 8 kHz, useful in eliminating low frequency noise and spurious signals which may be present at the input.
REV. A
-9-
AD600/AD602
+5V R3 46.4k +5V
R4 3.74k VG' RF INPUT C1LO A1HI A1LO GAT1 GAT2 A2LO A2HI C2LO C1HI A1CM A1OP VPOS VNEG A2OP A2CM C2HI C4 R1 0.1F 100
+5V DEC -5V DEC
AD590
300A (at 300K) FB
+5V
1 2 A1 3 4 REF 5 6 A2 7 8
16 15 14 13 12 11 10
0.1F
C2 1F Q1 2N3904 C3 15pF R2 806 1%
+5V DEC
-5V DEC
C1 100pF
VPTAT RF OUTPUT
FB
0.1F
-5V POWER SUPPLY DECOUPLING NETWORK
AD600
9
Figure 15. This Accurate HF AGC Amplifier Uses Just Three Active Components
A simple half-wave detector is used, based on Q1 and R2. The average current into capacitor C2 is just the difference between the current provided by the AD590 (300 A at 300 K, 27C) and the collector current of Q1. In turn, the control voltage VG is the time integral of this error current. When VG (and thus the gain) is stable, the rectified current in Q1 must, on average, exactly balance the current in the AD590. If the output of A2 is too small to do this, VG will ramp up, causing the gain to increase, until Q1 conducts sufficiently. The operation of this control system will now be described in detail. First, consider the particular case where R2 is zero and the output voltage VOUT is a square wave at, say, 100 kHz, that is, well above the corner frequency of the control loop. During the time VOUT is negative, Q1 conducts; when VOUT is positive, it is cut off. Since the average collector current is forced to be 300 A, and the square wave has a 50% duty-cycle, the current when conducting must be 600 A. With R2 omitted, the peak value of VOUT would be just the VBE of Q1 at 600 A (typically about 700 mV) or 2 VBE peak-to-peak. This voltage, hence the amplitude at which the output stabilizes, has a strong negative temperature coefficient (TC), typically -1.7 mV/C. While this may not be troublesome in some applications, the correct value of R2 will render the output stable with temperature. To understand this, first note that the current in the AD590 is closely proportional to absolute temperature (PTAT). (In fact, this IC is intended for use as a thermometer.) For the moment, continue to assume that the signal is a square wave. When Q1 is conducting, VOUT is the now the sum of VBE and a voltage which is PTAT and which can be chosen to have an equal but opposite TC to that of the base-to-emitter voltage. This is actually nothing more than the "bandgap voltage reference" principle in thinly veiled disguise! When we choose R2 such that the sum of the voltage across it and the VBE of Q1 is close to the bandgap voltage of about 1.2 V, VOUT will be stable over a wide range of temperatures, provided, of course, that Q1 and the AD590 share the same thermal environment.
Since the average emitter current is 600 A during each halfcycle of the square wave, a resistor of 833 would add a PTAT voltage of 500 mV at 300 K, increasing by 1.66 mV/C. In practice, the optimum value of R2 will depend on the transistor used, and, to a lesser extent, on the waveform for which the temperature stability is to be optimized; for the devices shown and sine wave signals, the recommended value is 806 . This resistor also serves to lower the peak current in Q1 and the 200 Hz LP filter it forms with C2 helps to minimize distortion due to ripple in VG. Note that the output amplitude under sine wave conditions will be higher than for a square wave, since the average value of the current for an ideal rectifer would be 0.637 times as large, causing the output amplitude to be 1.88 (= 1.2/0.637) V, or 1.33 V rms. In practice, the somewhat nonideal rectifier results in the sine wave output being regulated to about 1.275 V rms. An offset of +375 mV is applied to the inverting gain-control inputs C1LO and C2LO. Thus the nominal -625 mV to +625 mV range for VG is translated upwards (at VG) to -0.25 V for minimum gain to +1 V for maximum gain. This prevents Q1 from going into heavy saturation at low gains and leaves sufficient "headroom" of 4 V for the AD590 to operate correctly at high gains when using a +5 V supply. In fact, the 6 dB interstage attenuator means that the overall gain of this AGC system actually runs from -6 dB to +74 dB. Thus, an input of 2 V rms would be required to produce a 1 V rms output at the minimum gain, which exceeds the 1 V rms maximum input specification of the AD600. The available gain range is therefore 0 dB to 74 dB (or, X1 to X5000). Since the gain scaling is 15.625 mV/dB (because of the cascaded stages) the minimum value of VG is actually increased by 6 x 15.625 mV, or about 94 mV, to -156 mV, so the risk of saturation in Q1 is reduced.
-10-
REV. A
AD600/AD602
The emitter circuit of Q1 is somewhat inductive (due its finite ft and base resistance). Consequently, the effective value of R2 increases with frequency. This would result in an increase in the stabilized output amplitude at high frequencies, but for the addition of C3, determined experimentally to be 15 pF for the 2N3904 for maximum response flatness. Alternatively, a faster transistor can be used here to reduce HF peaking. Figure 16 shows the ac response at the stabilized output level of about 1.3 V rms. Figure 17 demonstrates the output stabilization for sine wave inputs of 1 mV to 1 V rms at frequencies of 100 kHz, 1 MHz and 10 MHz
+5V AD590 TO AD600 PIN 16 C2 1F Q1 2N3904 R2B C3 15pF TO AD600 PIN 11 R2A VPTAT R2 = R2A R2B 806 RF OUTPUT 300A (at 300K)
AGC OUTPUT CHANGE - dB
Figure 18. Modification in Detector to Raise Output to 2 V RMS
A Wide Range, RMS-Linear dB Measurement System (2 MHz AGC Amplifier with RMS Detector)
3dB
0.1
1
10 FREQUENCY - MHz
100
Figure 16. AC Response at the Stabilized Output Level of 1.3 V RMS
Monolithic rms-dc converters provide an inexpensive means to measure the rms value of a signal of arbitrary waveform, and they also may provide a low accuracy logarithmic ("decibelscaled") output. However, they have certain shortcomings. The first of these is their restricted dynamic range, typically only 50 dB. More troublesome is that the bandwidth is roughly proportional to the signal level; for example, the AD636 provides a 3 dB bandwidth of 900 kHz for an input of 100 mV rms, but has a bandwidth of only 100 kHz for a 10 mV rms input. Its logarithmic output is unbuffered, uncalibrated and not stable over temperature; considerable support circuitry, including at least two adjustments and a special high TC resistor, is required to provide a useful output. All of these problems can be eliminated using an AD636 as merely the detector element in an AGC loop, in which the difference between the rms output of the amplifier and a fixed dc reference are nulled in a loop integrator. The dynamic range and the accuracy with which the signal can be determined are now entirely dependent on the amplifier used in the AGC system. Since the input to the rms-dc converter is forced to a constant amplitude, close to its maximum input capability, the bandwidth is no longer signal dependent. If the amplifier has an exactly exponential ("linear-dB") gain-control law, its control voltage VG is forced by the AGC loop to be have the general form:
RELATIVE OUTPUT - dB
+0.2 100kHz 0 1MHz -0.2 -0.4 10MHz
0.001
0.01
0.1
1
INPUT AMPLITUDE - Volts RMS
Figure 17. Output Stabilization vs. RMS Input for Sine Wave Inputs at 100 kHz, 1 MHz, and 10 MHz
VOUT =VSCALE log 10
V IN (RMS ) VREF
(4)
While the "bandgap" principle used here sets the output amplitude to 1.2 V (for the square wave case), the stabilization point can be set to any higher amplitude, up to the maximum output of (VS - 2) V which the AD600 can support. It is only necessary to split R2 into two components of appropriate ratio whose parallel sum remains close to the zero-TC value of 806 . This is illustrated in Figure 18, which shows how the output can be raised, without altering the temperature stability.
Figure 19 shows a practical wide dynamic range rms-responding measurement system using the AD600. Note that the signal output of this system is available at A2OP, and the circuit can be used as a wideband AGC amplifier with an rms-responding detector. This circuit can handle inputs from 100 V to 1 V rms with a constant measurement bandwidth of 20 Hz to 2 MHz, limited primarily by the AD636 rms converter. Its logarithmic output is a loadable voltage, accurately calibrated to 100 mV/dB, or 2 V per decade, which simplifies the interpretation of the reading when using a DVM, and is arranged to be -4 V for an input of 100 V rms input, zero for 10 mV, and +4 V for a 1 V rms input. In terms of Equation 4, VREF is 10 mV and VSCALE is 2 V. -11-
REV. A
AD600/AD602
VRMS
AF/RF OUTPUT C1 0.1F C4 4.7F +6V DEC C1LO A1HI R2 200 A1LO 3 GAT1 R3 133k GAT2 A2LO A2HI U3A 1/2 AD712 VG 15.625mV/dB R4 3.01k C2LO 4 REF 5 6 A2 7 8 10 9 C1HI 16 15 A1 14 13 12 11 A1CM NC A1OP -6V DEC VPOS VNEG A2OP A2CM C2HI U3B 1/2 AD712 +6V DEC -6V DEC C2 2F FB 1 2 VINP
CAL 0dB
+6V
INPUT 1V RMS MAX R1 (SINE WAVE) 115
1 2
U2 AD636
VPOS 14 13 NC 12 NC 11 NC +6V DEC
0.1F
3 VNEG 4 CAVG NC 5 NC 6 7 VLOG BFOP BFIN
-6V DEC R7 56.2k FB 0.1F
COMM 10 LDLO VRMS 9 8
R6 3.16k
-6V POWER SUPPLY DECOUPLING NETWORK +316.2mV C3 1F VOUT
U1 AD600
R5 16.2k
+100mV/dB 0V = 0dB (AT 10mV RMS)
NC = NO CONNECT
Figure 19. The Output of This Three-IC Circuit Is Proportional to the Decibel Value of the RMS Input
Note that the peak "log output" of 4 V requires the use of 6 V supplies for the dual op amp U3 (AD712) although lower supplies would suffice for the AD600 and AD636. If only 5 V supplies are available, it will be either necessary to use a reduced value for VSCALE (say 1 V, in which case the peak output would be only 2 V) or restrict the dynamic range of the signal to about 60 dB. As in the previous case, the two amplifiers of the AD600 are used in cascade. However, the 6 dB attenuator and low-pass filter found in Figure 1 are replaced by a unity gain buffer amplifier U3A, whose 4 MHz bandwidth eliminates the risk of instability at the highest gains. The buffer also allows the use of a high impedance coupling network (C1/R3) which introduces a high-pass corner at about 12 Hz. An input attenuator of 10 dB (X0.316) is now provided by R1 + R2 operating in conjunction with the AD600's input resistance of 100 . The adjustment provides exact calibration of the logarithmic intercept VREF in critical applications, but R1 and R2 may be replaced by a fixed resistor of 215 if very close calibration is not needed, since the input resistance of the AD600 (and all other key parameters of it and the AD636) are already laser trimmed for accurate operation. This attenuator allows inputs as large as 4 V to be accepted, that is, signals with an rms value of 1 V combined with a crest factor of up to 4. The output of A2 is ac coupled via another 12 Hz high-pass filter formed by C2 and the 6.7 k input resistance of the AD636. The averaging time constant for the rms-dc converter is determined by C4. The unbuffered output of the AD636 (at Pin 8) is compared with a fixed voltage of +316 mV set by the positive supply voltage of +6 V and resistors R6 and R7. (VREF is proportional to this voltage, and systems requiring greater calibration accuracy should replace the supply dependent reference with a more stable source.)
Any difference in these voltages is integrated by the op amp U3B, with a time constant of 3 ms formed by the parallel sum of R6/R7 and C3. Now, if the output of the AD600 is too high, V rms will be greater than the "setpoint" of 316 mV, causing the output of U3B--that is, VOUT--to ramp up (note that the integrator is noninverting). A fraction of VOUT is connected to the inverting gain-control inputs of the AD600, so causing the gain to be reduced, as required, until V rms is exactly equal to 316 mV, at which time the ac voltage at the output of A2 is forced to be exactly 316 mV rms. This fraction is set by R4 and R5 such that a 15.625 mV change in the control voltages of A1 and A2--which would change the gain of the cascaded amplifiers by 1 dB--requires a change of 100 mV at VOUT. Notice here that since A2 is forced to operate at an output level well below its capacity, waveforms of high crest factor can be tolerated throughout the amplifier. To check the operation, assume an input of 10 mV rms is applied to the input, which results in a voltage of 3.16 mV rms at the input to A1, due to the 10 dB loss in the attenuator. If the system operates as claimed, VOUT (and hence VG) should be zero. This being the case, the gain of both A1 and A2 will be 20 dB and the output of the AD600 will therefore be 100 times (40 dB) greater than its input, which evaluates to 316 mV rms, the input required at the AD636 to balance the loop. Finally, note that unlike most AGC circuits, needing strong temperature compensation for the internal "kT/q" scaling, these voltages, and thus the output of this measurement system, are temperature stable, arising directly from the fundamental and exact exponential attenuation of the ladder networks in the AD600. Typical results are presented for a sine wave input at 100 kHz. Figure 20 shows that the output is held very close to the setpoint of 316 mV rms over an input range in excess of 80 dB.
-12-
REV. A
AD600/AD602
(This system can, of course, be used as an AGC amplifier, in which the rms value of the input is leveled.) Figure 21 shows the "decibel" output voltage. More revealing is Figure 22, which shows that the deviation from the ideal output predicted by Equation 1 over the input range 80 V to 500 mV rms is within
450 425 400 375 350
0.5 dB, and within 1 dB for the 80 dB range from 80 V to 800 mV. By suitable choice of the input attenuator R1 + R2, this could be centered to cover any range from 25 mV to 250 mV to, say, 1 mV to 10 V, with appropriate correction to the value of VREF. (Note that VSCALE is not affected by the changes in the range.) The gain ripple of 0.2 dB seen in this curve is the result of the finite interpolation error of the X-AMP. Note that it occurs with a periodicity of 12 dB--twice the separation between the tap points (because of the two cascaded stages). This ripple can be canceled whenever the X-AMP stages are cascaded by introducing a 3 dB offset between the two pairs of control voltages. A simple means to achieve this is shown in Figure 23: the voltages at C1HI and C2HI are "split" by 46.875 mV, or 1.5 dB. Alternatively, either one of these pins can be individually offset by 3 dB and a 1.5 dB gain adjustment made at the input attenuator (R1 + R2).
C1HI 16 15 A1CM NC -6V DEC +6V DEC -6V DEC C2 2F NC NC
VOUT - mV
325 300 275 250 225 200 175 150 10V 100V 1mV 10mV 100mV 1V 10V
1 2
VINP
INPUT SIGNAL -V RMS
14 A1OP
3 VNEG 4 CAVG 5 6 7 VLOG BFOP BFIN
Figure 20. The RMS Output of A2 Is Held Close to the "Setpoint" 316 mV for an Input Range of Over 80 dB
5 4 3 2 VOUT - Volts 1
U1 AD600
13 12 11 10 9
VPOS VNEG A2OP A2CM C2HI
U2 AD636
-46.875mV -6V DEC
+46.875mV +6V DEC
10k
78.7
78.7
10k
NC = NO CONNECT
3dB OFFSET MODIFICATION
0 -1 -2 -3 -4 -5 10V
Figure 23. Reducing the Gain Error Ripple
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 21. The dB Output of Figure 19's Circuit Is Linear Over an 80 dB Range
2.5 2.0 1.5
The error curve shown in Figure 24 demonstrates that over the central portion of the range the output voltage can be maintained very close to the ideal value. The penalty for this modification is the higher errors at the extremities of the range. The next two applications show how three amplifier sections can be cascaded to extend the nominal conversion range to 120 dB, with the inclusion of simple LP filters of the type shown in Figure 15. Very low errors can then be maintained over a 100 dB range.
2.5 2.0 1.5
OUTPUT ERROR - dB
0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 10V
OUTPUT ERROR - dB
100V 1mV 10mV 100mV 1V 10V
1.0
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
INPUT SIGNAL - V RMS
Figure 22. Data from Figure 20 Presented as the Deviation from the Ideal Output Given in Equation 4
Figure 24. Using the 3 dB Offset Network, the Ripple Is Reduced
REV. A
-13-
AD600/AD602
INPUT 1V RMS MAX (SINE WAVE) C1LO A1HI A1LO 3 GAT1 GAT2 A2LO A2HI C2LO 4 REF 5 6 A2 7 8 10 9 1 2 A1 14 13 12 11 16 15 C1HI A1CM A1OP VPOS VNEG A2OP A2CM C2HI R4 133k C3 220pF U3B 1/4 AD713 +5V DEC -5V DEC C1 0.1F U3A 1/4 AD713 C2 0.1F R5 1.58k R2 487 R3 200 C1LO A1HI A1LO 3 GAT1 GAT2 A2LO A2HI C2LO 4 REF 5 6 A2 7 8 10 9 1 2 A1 14 13 12 16 15 C1HI A1CM A1OP VPOS VNEG +5V DEC -5V DEC C4 2F
VOUT
R1 133k
11 A2OP A2CM C2HI
U1 AD600
U2 AD600
+5V -2dB -62.5mV FB +5V DEC 0.1F -5V R6 10k 0.1F C5 22F -5V POWER SUPPLY DECOUPLING NETWORK 1 +5V DEC NC R15 19.6k R16 6.65k R14 301k -5V DEC 2 VPOS 14 13 NC 12 NC 11 NC COMM 10 LDLO VRMS 9 8 U3C 1/4 AD713 VLOG R10 3.16k R11 46.4k C6 4.7F +5V DEC R7 127 R8 127 R9 10k 0dB +2dB +62.5mV +5V
-5V DEC FB
VINP
U4 AD636
3 VNEG 4 CAVG
Q1 2N3906
NC NC
5 6 7
VLOG BFOP BFIN
R13 3.01k
R12 11.3k
+316.2mV
NC = NO CONNECT
Figure 25. RMS Responding AGC Circuit with 100 dB Dynamic Range
100 dB to 120 dB RMS Responding Constant Bandwidth AGC Systems with High Accuracy dB Outputs
The next two applications double as both AGC amplifiers and measurement systems. In both, precise gain offsets are used to achieve either (1) a very high gain linearity of 0.1 dB over the full 100 dB range, or (2) the optimal signal-to-noise ratio at any gain.
A 100 dB RMS/AGC System with Minimal Gain Error (Parallel Gain with Offset)
remarkably low 0.25 dB over the 108 dB range from 6 V to 1.5 V rms. However, with the gain offsets connected, the gain linearity remains under 0.1 dB over the specified 100 dB range (Figure 28).
5 4 LOGARITHMIC OUTPUT - Volts 3 2 1 0 -1 -2 -3 -4 -5 1V
Figure 25 shows an rms-responding AGC circuit, which can equally well be used as an accurate measurement system. It accepts inputs of 10 V to 1 V rms (-100 dBV to 0 dBV) with generous overrange. Figure 26 shows the logarithmic output, VLOG, which is accurately scaled 1 V per decade, that is, 50 mV/dB, with an intercept (VLOG = 0) at 3.16 mV rms (-50 dBV). Gain offsets of 2 dB have been introduced between the amplifiers, provided by the 62.5 mV introduced by R6-R9. These offsets cancel a small gain ripple which arises in the X-AMP from its finite interpolation error, which has a period of 18 dB in the individual VCA sections. The gain ripple of all three amplifier sections without this offset (in which case the gain errors simply add) is shown in Figure 27; it is still a
10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 26. VLOG Plotted vs. VIN for Figure 25`s Circuit Showing 120 dB AGC Range
-14-
REV. A
AD600/AD602
2.0 1.5 1.0
0.5 0.1 0 -0.1 -0.5 -1.0 -1.5 -2.0 1V
The rms value of VLOG is generated at Pin 8 of the AD636; the averaging time for this process is determined by C5, and the value shown results in less than 1% rms error at 20 Hz. The slowly varying V rms is compared with a fixed reference of 316 mV, derived from the positive supply by R10/R11. Any difference between these two voltages is integrated in C6, in conjunction with op amp U3C, the output of which is VLOG. A fraction of this voltage, determined by R12 and R13, is returned to the gain control inputs of all AD600 sections. An increase in VLOG lowers the gain, because this voltage is connected to the inverting polarity control inputs. Now, in this case, the gains of all three VCA sections are being varied simultaneously, so the scaling is not 32 dB/V but 96 dB/ V, or 10.42 mV/dB. The fraction of VLOG required to set its scaling to 50 mV/dB is therefore 10.42/50, or 0.208. The resulting full-scale range of VLOG is nominally 2.5 V. This scaling was chosen to allow the circuit to operate from 5 V supplies. Optionally, the scaling could be altered to 100 mV/dB, which would be more easily interpreted when VLOG is displayed on a DVM, by increasing R12 to 25.5 k. The full-scale output of 5 V then requires the use of supply voltages of at least 7.5 V. A simple attenuator of 16.6 1.25 dB is formed by R2/R3 and the 100 input resistance of the AD600. This allows the reference level of the decibel output to be precisely set to zero for an input of 3.16 mV rms, and thus center the 100 dB range between 10 V and 1 V. In many applications R2/R3 may be replaced by a fixed resistor of 590 . For example, in AGC applications, neither the slope nor the intercept of the logarithmic output is important. A few additional components (R14-R16 and Q1) improve the accuracy of VLOG at the top end of the signal range (that is, for small gains). The gain starts rolling off when the input to the first amplifier, U1A, reaches 0 dB. To compensate for this nonlinearity, Q1 turns on at VLOG ~ +1.5 V and increases the feedback to the control inputs of the AD600s, thereby needing a smaller voltage at VLOG to maintain the input to the AD636 to the setpoint of 316 mV rms.
A 120 dB RMS/AGC System with Optimal S/N Ratio (Sequential Gain)
GAIN ERROR - dB
10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 27. Gain Error for Figure 25 Without the 2 dB Offset Modification
2.0 1.5 1.0
GAIN ERROR - dB
0.5 0.1 0 -0.1 -0.5 -1.0 -1.5 -2.0 1V
10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 28. Adding the 2 dB Offsets Improves the Linearization
The maximum gain of this circuit is 120 dB. If no filtering were used, the noise spectral density of the AD600 (1.4 nV/Hz) would amount to an input noise of 8.28 V rms in the full bandwidth (35 MHz). At a gain of one million, the output noise would dominate. Consequently, some reduction of bandwidth is mandatory, and in the circuit of Figure 25 it is due mostly to a single-pole low-pass filter R5/C3, which provides a -3 dB frequency of 458 kHz, which reduces the worst-case output noise (at VAGC) to about 100 mV rms at a gain of 100 dB. Of course, the bandwidth (and hence output noise) could be easily reduced further, for example, in audio applications, merely by increasing C3. The value chosen for this application is optimal in minimizing the error in the VLOG output for small input signals. The AD600 is dc-coupled, but even miniscule offset voltages at the input would overload the output at high gains, so high-pass filtering is also needed. To provide operation at low frequencies, two simple zeros at about 12 Hz are provided by R1/C1 and R4/C2; op amp sections U3A and U3B (AD713) are used to provide impedance buffering, since the input resistance of the AD600 is only 100 . A further zero at 12 Hz is provided by C4 and the 6.7 k input resistance of the AD636 rms converter.
In the last case, all gains were adjusted simultaneously, resulting in an output signal-to-noise ratio (S/N ratio) which is always less than optimal. The use of sequential gain control results in a major improvement in S/N ratio, with only a slight penalty in the accuracy of VLOG, and no penalty in the stabilization accuracy of VAGC. The idea is simply to increase the gain of the earlier stages first (as the signal level decreases) and thus maintain the highest S/N ratio throughout the amplifier chain. This can be easily achieved with the AD600 because its gain is accurate even when the control input is overdriven; that is, each gaincontrol "window" of 1.25 V is used fully before moving to the next amplifier to the right. Figure 29 shows the circuit for the sequential control scheme. R6 to R9 with R16 provide offsets of 42.14 dB between the individual amplifiers to ensure smooth transitions between the gain of each successive X-AMP, with the sequence of gain increase being U1A first, then U1B, and lastly U2A. The adjustable attenuator provided by R3 + R17 and the 100 input
REV. A
-15-
AD600/AD602
C1LO A1HI A1LO 3 GAT1 GAT2 A2LO A2HI C2LO 4 REF 5 6 A2 7 8 10 9 1 2 A1 14 13 12 11 C1HI 16 15 A1CM A1OP VPOS VNEG A2OP A2CM C2HI R4 133k C3 0.001F U3B 1/4 AD713 +6V DEC -6V DEC C1 0.1F U3A 1/4 AD713 C2 0.1F R5 5.36k R2 100 A1HI A1LO 3 GAT1 GAT2 A2LO A2HI C2LO 4 REF 5 6 A2 7 8 10 9 C1LO 1 2 A1 14 13 12 C1HI 16 15 A1CM A1OP VPOS VNEG +6V DEC -6V DEC C4 2F VOUT
R1 133k
11 A2OP A2CM C2HI
U1 AD600
0dB ADJUST
U2 AD600
R3 200
+6V R17 115 INPUT R6 3.4k R7 1k R8 294 R9 1k R16 287
C5 22F +6V DEC FB +6V DEC 1 NC -6V DEC 2 VINP
+6V
0.1F
U4 AD636
VPOS 14 13 NC 12 NC 11 NC R10 3.16k R11 56.2k C6 4.7F -6V DEC FB 0.1F
3 VNEG 4 CAVG NC NC 5 6 7 VLOG BFOP BFIN
-6V POWER SUPPLY DECOUPLING NETWORK
COMM 10 LDLO VRMS 9 8 U3C 1/4 AD713
+6V DEC R15 5.11k R14 7.32k R13 866 R12 1k
VLOG
+316.2mV
NC = NO CONNECT
Figure 29. 120 dB Dynamic Range RMS Responding Circuit Optimized for S/N Ratio
LOGARITHMIC OUTPUT - Volts
resistance of U1A as well as the fixed 6 dB attenuation provided by R2 and the input resistance of U1B are included both to set VLOG to read 0 dB when VIN is 3.16 mV rms and to center the 100 dB range between 10 V rms and 1 V rms input. R5 and C3 provide a 3 dB noise bandwidth of 30 kHz. R12 to R15 change the scaling from 625 mV/decade at the control inputs to 1 V/decade at the output and at the same time center the dynamic range at 60 dB, which occurs if the VG of U1B is equal to zero. These arrangements ensure that the VLOG will still fit within the 6 V supplies. Figure 30 shows VLOG to be linear over a full 120 dB range. Figure 31 shows the error ripple due to the individual gain functions which is bounded by 0.2 dB (dotted lines) from 6 V to 2 V. The small perturbations at about 200 V and 20 mV, caused by the impracticality of matching the gain functions perfectly, are the only sign that the gains are now sequential. Figure 32 is a plot of VAGC which remains very close to its set value of 316 mV rms over the full 120 dB range. To more directly compare the signal-to-noise ratios in the "simultaneous" and "sequential" modes of operation, all interstage attenuation was eliminated (R2 and R3 in Figure 25, R2 in Figure 29), the input of U1A was shorted, R5 was selected to provide a 20 kHz bandwidth (R5 = 7.87 k), and only the gain control was varied, using an external source. The rms value of the noise was then measured at VOUT and expressed as an S/N
5 4 3 2 1 0 -1 -2 -3 -4 -5 1V
10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 30. VLOG Is Essentially Linear Over the Full 120 dB Range
ratio relative to 0 dBV, this being almost the maximum output capability of the AD600. Results for the simultaneous mode can be seen in Figure 33. The S/ N ratio degreades uniformly as the gain is increased. Note that since the inverting gain control was used, the gain in this curve and in Figure 34 decreases for more positive values of the gain-control voltage. REV. A
-16-
AD600/AD602
2.0 1.5 1.0
GAIN ERROR - dB
0.5 0.2 0 -0.2 -0.5
In contrast, the S/N ratio for the sequential mode is shown in Figure 34. U1A always acts as a fixed noise source; varying its gain has no influence on the output noise. (This is a feature of the X-AMP technique.) Thus, for the first 40 dB of control range (actually slightly more, as explained below), when only this VCA section has its gain varied, the S/N ratio remains constant. During this time, the gains of U1B and U2A are at their minimum value of -1.07 dB.
90
-1.0
80
-1.5 -2.0 1V
70 60 50 40 30 20 10
10V
100V
1mV
10mV
100mV
1V
10V
INPUT SIGNAL - V RMS
Figure 31. The Error Ripple Due to the Individual Gain Functions
400
S/N RATIO - dB
350
0 -1.183 -0.558 0.067
0.692
1.317
1.942
2.567
3.192
3.817
GAIN ERROR - mV
CONTROL VOLTAGE, VC (31.25mV/dB) - Volts
300
Figure 34. S/N Ratio vs. Control Voltage for Sequential Gain Control (Figure 29)
250
200 1V
10V
100V
1mV
10mV
100mV
1V
10V
For the next 40 dB of control range, the gain of U1A remains fixed at its maximum value of 41.07 dB and only the gain of U1B is varied, while that of U2A remains at its minimum value of -1.07 dB. In this interval, the fixed output noise of U1A is amplified by the increasing gain of U1B and the S/N ratio progressively decreases. Once U1B reaches its maximum gain of 41.07 dB, its output also becomes a gain independent noise source; this noise is presented to U2A. As the control voltage is further increased, the gains of both U1A and U1B remain fixed at their maximum value of 41.07 dB, and the S/N ratio continues to decrease. Figure 34 clearly shows this, because the maximum S/N ratio of 90 dB is extended for the first 40 dB of input signal before it starts to roll off. This arrangement of staggered gains can be easily implemented because, when the control inputs of the AD600 are overdriven, the gain limits to its maximum or minimum values without side effects. This eliminates the need for awkward nonlinear shaping circuits that have previously been used to break up the gain range of multistage AGC amplifiers. It is the precise values of the AD600's maximum and minimum gain (not 0 dB and 40 dB but -1.07 dB and 41.07 dB) that explain the rather odd values of the offset values that are used.
INPUT SIGNAL - V RMS
Figure 32. VAGC Remains Nose to Its Setpoint of 316 mV RMS Over the Full 120 dB Range
90 80 70 60 50 40 30 20 10 0 -833.2 -625.0 -416.6 -208.3
S/N RATIO - dB
0
208.3
416.6
625.0
833.2
CONTROL VOLTAGE, VC (10.417mV/dB) - mV
Figure 33. S/N Ratio vs. Control Voltage for Parallel Gain Control (Figure 25)
The optimization of the output S/N ratio is of obvious value in AGC systems. However, in applications where these circuit are considered for their wide range logarithmic measurements capabilities, the inevitable degradation of the S/N ratio at high gains need not seriously impair their utility. In fact, the bandwidth of the circuit shown in Figure 25 was specifically chosen so as to improve measurement accuracy by altering the shape of the log error curve (Figure 31) at low signal levels.
REV. A
-17-
AD600/AD602-Typical Performance Characteristics
0.45 0.35 0.25
GAIN ERROR - dB
20dB 17dB
10dB 7dB
0.15 0.05 -0.05 -0.15
0 -45 -90
0 -45 -90
-0.25 -0.35 -0.45 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7
100k
GAIN CONTROL VOLTAGE - Volts
1M 10M FREQUENCY - Hz
100M
100k
1M
10M
100M
FREQUENCY - Hz
Figure 35. Gain Error vs. Gain Control Voltage
Figure 36. AD600 Frequency and Phase Response vs. Gain
Figure 37. AD602 Frequency and Phase Response vs. Gain
NEGATIVE OUTPUT VOLTAGE LIMIT - Volts
10.0 9.8 9.6
-1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 -3.2 -3.4 0 50 100 200 500 1000 2000 LOAD RESISTANCE -
GROUP DELAY - ns
9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 GAIN CONTROL VOLTAGE - Volts 0.7
VG =0V 10dB/DIV CENTER FREQ 1MHz 10kHz/DIV
Figure 38. AD600 and AD602 Typical Group Delay vs. VC
Figure 39. Third Order Intermodulation Distortion, VOUT = 2 V p-p, RL = 500
Figure 40. Typical Output Voltage vs. Load Resistance (Negative Output Swing Limits First)
102
6 GAIN=40dB
OUTPUT OFFSET VOLTAGE - mV
101 100 INPUT IMPEDANCE - 99 98 97 96 95 94 93 92 100k
5
1V VOUT 1S
4 3 2 1 0 -1 -2 -3 -4 -0.7 AD602
AD600
100 90
GAIN=20dB GAIN=0dB
OUTPUT
10 0%
INPUT
1V VC
1M 10M FREQUENCY - Hz
100M
-0.5 -0.3 -0.1 0.1 0.3 0.5 GAIN CONTROL VOLTAGE - Volts
0.7
Figure 41. Input Impedance vs. Frequency
Figure 42. Output Offset vs. Gain Control Voltage (Control Channel Feedthrough)
Figure 43. Gain Control Channel Response Time. Top: Output Voltage, 2 V max, Bottom: Gain Control Voltage VC = 625 mV
-18-
REV. A
AD600/AD602
50mV
100 90 100 90
50mV
100 90
1V
OUTPUT
OUTPUT OUTPUT
10 0%
10 0%
10 0%
INPUT
INPUT
5V
100nS
5V
100nS
100mV
INPUT
500nS
Figure 44. Gating Feedthrough to Output, Gating Off to On
Figure 45. Gating Feedthrough to Output, Gating On to Off
Figure 46. Transient Response, Medium and High Gain
500mV
100 90 100 90
1V
100 90
500mV
OUTPUT
OUTPUT
OUTPUT
10 0%
10 0%
10 0%
INPUT
INPUT
INPUT
1V
200nS
200mV
500nS
1V
500nS
Figure 47. Input Stage Overload Recovery Time
Figure 48. Output Stage Overload Recovery Time
Figure 49. Transient Response Minimum Gain
+10 +5 0 -5 AD600: G=20dB AD602: G=10dB BOTH: VCM =100mV RMS VS =5V R L=500 TA =25C AD600
+20 +10 0
+10 0 -10
AD600: CH1 G=40dB, VIN =0 CH2 G=20dB, VIN =100mV AD602: CH1 G=30dB, VIN =0 CH2 G=10dB, VIN =316mV BOTH: VOUT =1V RMS, R S =50, R L=500 CH1 VOUT CROSSTALK=20log{CH2 V IN
CROSSTALK - dB
-10
PSRR - dB
AD600
-20 -30 -40 -50 -60 -70 -80
AD600
CMRR - dB
-10 -15 -20 -25 -30 -35 -40 1k
-20 -30 -40 -50
AD600: G=40dB AD602: G=30dB BOTH: R L=500 VIN =0V RS =50
}
AD602
AD602
AD602
-60 -70
10k
100k 1M 10M FREQUENCY -- Hz
100M
-80 100k
1M 10M FREQUENCY - Hz
100M
-90 100k
1M 10M FREQUENCY - Hz
100M
Figure 50. CMRR vs. Frequency
Figure 51. PSRR vs. Frequency
Figure 52. Crosstalk Between A1 and A2 vs. Frequency
REV. A
-19-
AD600/AD602
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16) Package
16 9
0.25 0.31 (6.35) (7.87)
1 8
0.87 (22.1) MAX 0.035 (0.89) 0.18 (4.57) 0.125 (3.18) MIN 0.033 (0.84) 0.1 (2.54) 0.18(4.57) MAX 0.011 (0.28) 0.3 (7.62) 0.018 (0.46)
16-Pin SOIC (R-16) Package
16
9
0.299 (7.60)
0.419 (10.65)
1
8
0.012 (0.3)
0.413 (10.50) 0.104 (2.65) 0.05 (1.27) REF 0.019 (0.49)
0.030 (0.75)
0.013 (0.32)
0.042 (1.07)
16-Pin Cerdip (Q-16) Package
0.005 (0.13) MIN 0.080 (2.03) MAX
16 PIN 1 1
9 0.310 (7.87) 0.220 (5.59) 8 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38)
0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18)
0.150 (3.81) MIN SEATING PLANE
0.015 (0.38) 0.008 (0.20) 15
0.023 (0.58) 0.014 (0.36)
0.100 (2.54) BSC
0.070 (1.78) 0.030 (0.76)
0
-20-
REV. A
PRINTED IN U.S.A.
C1664-24-4/92

▲Up To Search▲

Price & Availability of AD602

	To Download AD602 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .